1) Field of the Invention
This invention relates in general to semiconductor devices, methods for designing semiconductor devices, masks and mask designs, and more particularly, to semiconductor designs, methods and devices with slots in active areas.
2) Description of the Prior Art
Semiconductor integrated circuits and printed circuit electronic packages are generally structures comprised of several layers of conducting, insulating and other materials that are structured in the horizontal dimension by fabrication processes that transfer patterns defined in physical designs or layouts. A layout consists of a set of planar geometric shapes in several layers. These physical designs or layouts are typically represented as computer data consisting of two dimensional shapes in a hierarchical data structure that exploit the repetitive structure usually found in such circuits and packages. The design or layout files are then converted into pattern generator files that are used to produce-patterns called masks.
In some cases, the action of the fabrication process is affected by the design patterns being transferred to the physical materials. For example, the local pattern density of the design, i.e., the fraction of area over which material is deposited (or removed) can affect the shapes and dimensions of features, with the “locality extent” dependent on the specific fabrication process. A special process that may be affected by local pattern density is chemical-mechanical (so called “chemech”) polishing (CMP). CMP is used to planarize semiconductor substrates. Planarization is becoming more and more important as the numbers of layers used to form a semiconductor device increases. Nonplanar substrates show many problems including difficulties in patterning a photoresist layer, formation of a void within a film during film deposition, and incomplete removal of a layer during an etch process leaving residual portions of the layer.
However, CMP has the disadvantage of showing so called “dishing” when polishing areas of wide metal. Especially in case copper is used this effect will result in nonplanar surfaces of the substrate, leading to the difficulties mentioned above.
FIG. 1 shows two situations where dishing occurs. Within smaller wires (A) dishing can be neglected to a certain degree, whereas for wide wires (B) it shows big impact on the metal's resistance and on the manufacturability.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 5,602,423(Jain) that shows a metal line inlaid with slots or pillars.
U.S. Pat. No. 6,403,389b1(Chang et al.) shows a method for forming slots in conductors to prevent dishing during chemical-mechanical polish.
U.S. Pat. No. 6,495,907b1(Jain et al.) shows a conductor reticulation and process.
U.S. Pat. No. 5,671,152(Lavin et al.) shows a method for generating negative fill shapes for metal lines.
U.S. Pat. No. 6,319,818b1(Stamper) shows a method to add holes to metal lines to improve CMP planarization.
U.S. Pat. No. 6,094,812(English et al. ) shows a method to split up metal lines.
U.S. Pat. No. 5,923,563(Lavin et al.) shows a method to add fill shapes.
U.S. Pat. No. 2002/0199162A1(Ramaswamy et al.) Dec. 15, 2002 discloses a method for a fill pattern.
U.S. Pat. No. 6,396,158B1(Travis) shows a method for designing dummy feature in a mask layout.
U.S. Pat. No. 6,081,272(Morimoto et al.) shows a method of sizing and position dummy structures.
Andrew B. Kahng et al., “Filling and Slotting: Analysis and Algorithms”, ISPD 98 Monterey Calif. USA, pp. 95–102.
However, these designs, methods and device can be improved upon.